Many integrated circuit (IC) designs require capacitors. Where feasible they are included as on-chip devices. Commonly used structures employ metal plates separated by a deposited dielectric. Polycrystalline silicon (polysilicon) plates have proven useful with deposited or thermally grown dielectrics. In addition metal-silicon plates, called silicides, are good electrical conductors, refractory in nature and have proven useful in fabricating capacitors. Polysilicon in combination with refractory metal silicides can form what is called a polycide which is also useful in forming capacitor plates.
While such capacitors can be fabricated to close tolerances, they commonly have an unacceptably high voltage coefficient of capacitance. This voltage coefficient varies the capacitance value with applied voltage. Where the capacitor value must be highly accurate, as in D/A and A/D converter applications, this voltage sensitivity can be a problem. In order to provide a 16-bit A/D conversion accuracy, the capacitor must not vary more than about .+-.15 ppm over a voltage range of .+-.20 volts. Using typical prior art construction, capacitor shifts of over 2500 ppm are common over the .+-.20 volt range. Clearly, such a shift makes the capacitor unsuitable for the converter applications involving more than about 10-bit accuracy.
U.S. Pat. No. 4,335,371 was issued to the assignee of the present invention on June 15, 1982. This patent shows the use of A/D converter circuits in which capacitor charge balancing is used in the comparator circuits. The teaching in this patent is incorporated herein by reference.